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AMS verification and modeling - Staff Engineer

Bengaluru, KA
Job Code:
  • IT
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Job Details

Execute on pre-silicon verification of mixed signal IP products. Create re-usable test benches using advanced verification methodologies (like UVM, OVM, Wreal etc.) with emphasis towards behavioral modeling of analog blocks, closed-loop simulation with digital design and analog behavioral models and/or transistors by using Cadence Virtuoso schematic editor and automated& coverage-driven verification.QualificationsBSEE with 7+ years of experience in Mixed Signal Design Verification or MSEE with 5+ years of experience in Mixed Signal Design Verification.Experienced with successful tapeout of mixed-signal products from verification plan and automated test bench development, coverage models, assertion based and automated random verification methodologies like UVM, OVM with focus towards closed-loop simulations using WReal or Behavioral Modeling of Analog blocks, Mixed-Signal circuits and systems.Experienced in creating verification plans, scripting & tool usage with familiarity on using SystemVerilog, Verilog-AMS, Verilog-A, WReal & Verilog behavioral modeling as event based models, Cadence Virtuoso schematic editor, PERL, shell scripting, protocols and standards like Ethernet, PCIe, SATA, Serdes, MIPI, USB, DisplayPort, HDMI, PLL and ADC and in general on communication, consumer & industrial related standards etc.Preferred Skills Assertion methodology in Analog, and Formal VerificationAnalog transistor-level design or SPICE simulation experienceVerilog-AMS wreal, Verilog-A, SystemVerilog behavioral modeling for analog blocks and Behavioral vs. Schematic equivalence checkMixed Signal Verification Test Bench components developmentFamiliarity with Protocols and standards like Ethernet, PCIe, SATA, Serdes, MIPI
Degree: MCA/ PGDCA | ME/ M.Tech./ MS (Engg/ Sciences)

Additional Degree: BE/ B.Tech (Engineering)

Experience: 6-10


H/W Installation/Maintenance | Hardware Design | RF Engineering
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