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Asic Verification Engineers - SV+OVM/UVM


Source:
TIMESJOBS.COM
Location:
Bengaluru, KA
Date:
08-11-2016
Job Code:
58226412
Categories:
  • IT
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Job Details

Experience 4-8 years Candidate will be involved in developing Testbench for the Block / Cluster, Testcases, Tesplans and Functional and Code coverage closure activities and reviews of documents and code. Candidate will be individually responsible for successful delivery to clients for given tasks/module of Testbench/Testcases. Candidate will responsible for the Client Support activities which conference call on reviews and Bug closure. At-least 1.5 years of experience in System Verilog HVL. At-least 1 year of experience in OVM/UVM/VMM/Test Harness. Experience in developing test and coverage plan and Verification environment.Knowledge of industry standard protocols like Ethernet, PCIe, MIPI, AXI-AHB Bus etc. will be added advantage.
Additional Degree: BE/ B.Tech (Engineering)

Experience: 4-8

Requirements

H/W Installation/Maintenance | Hardware Design | Network Planning | RF Engineering
Applying for this job will take you to an external site

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