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Chip Lead (Physical Design) - US Captive


Source:
TIMESJOBS.COM
Location:
Bengaluru, KA
Date:
11-11-2016
Job Code:
58218260
Categories:
  • IT
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Job Details

Location BengaluruExperience 7 - 13 yearsRequirements BS / MS in EE/CSE from a reputed University Good knowledge of VLSI process and device characteristics, to make optimal trade-off between performance and power. Good knowledge of standard cell libraries circuit design and cell Good understanding of static timing analysis (STA), EM/IR and sign-off Strong hands-on experience with- Full Chip Implementationo Chip Level floor planning, partition, pin assignmento Power planning, Bump Planning, Pad Ring Creation.o Integration of different sub-blocks and custom macros/IPs.o Top level timing closure.o Physical Verification EDA Tool Expertise- Encounter Digital Implementation System , PrimeTime-SI, StarXT, Calibre, Conformal LEC Good software and scripting skills (perl, python, tcl). Must have good communication skills and the ability and desire to work as a team.Job Description Work on top level implementation of hierarchical chipo Chip Level floor planning, partition, pin assignment.o Power planning, bump planning, pad ring creation.o Integration of different sub-blocks and custom macros/IPs.o Top level timing closure.o Physical Verification. Develop, support and maintain physical design flows and methodologies Work closely with the design team to accomplish the objectives.email to aniruddh@onssearch.in
Degree: M.Com. (Commerce) | M.Pharm. (Pharmacy) | M.Sc. (Science) | MA (Arts) | MBA/ PGDM | MCA/ PGDCA

Additional Degree: BE/ B.Tech (Engineering)

Experience: 8-13

Requirements

Hardware Design
Applying for this job will take you to an external site

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