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DESIGN FOR TEST (JUNIOR TO MID LEVEL)


Source:
TIMESJOBS.COM
Location:
Bengaluru, KA
Date:
10-11-2016
Job Code:
58245820
Categories:
  • IT
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Job Details

Job DescriptionDigital, Mixed-Signal SOC/IP/Sub-System DFTIndividual contributorBe able to work in a teamBe able to work with little or no supervisionSeek technical support as requiredShould have sound understanding of all the design for test requirementsShould be able to comprehend DFT architecture, architecture limitations, schedule, volume of the task(s).Aware of all the aspects relating to Scan/ATPGScan synthesis, coverage metrics by fault-models stuck-at, delay & Bridging,Memory bistTest power estimation, Bounday scan, IDDQ, IO testing, Mixed-signal IP testing, Analog IP testing,Post-Silicon debug and supportKnowledge of test STADebug skills and Automation savvy.Good understanding of Gate-Level simulations and its nuancesTranslate tool generated patterns to ATE platformBe able to help in silicon debug both on ATE and at system level Responsibilities Working knowledge of ATPG tools Tetramax/Fastscan/Encounter.Working knowledge of any or all of the simulation tools/environment
Degree: ME/ M.Tech./ MS (Engg/ Sciences)

Additional Degree: BE/ B.Tech (Engineering)

Experience: 2-7

Requirements

Hardware Design | RF Engineering
Applying for this job will take you to an external site

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