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DFT Engineer


Source:
TIMESJOBS.COM
Location:
Bengaluru, KA
Date:
11-11-2016
Job Code:
58250516
Categories:
  • IT
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Job Details

This position is in Intel's PEG Centralized Design-for-Test team. This team is responsible for driving consistent DFT architecture, methodology, and flows across various product segments. Candidates should be well versed with industry standard DFT techniques such as scan/ATPG, memory Built-in-Self-Test (MBIST), Test Access Port (TAP), boundary scan, I/O testing, etc. The role also involves supporting multiple design teams and cross functional activities working with debug, post silicon, and bring up teams.Qualifications BSEE and 8+ years in Design and DFT or MSEE and 6+ years in DFT. The candidate should be well versed with Scan, ATPG, Memory test, IO testing. The candidate should also have experience in DFT EDA tools, architectures, IP development, vector generation, bring-up of Si to production ramp.Inside this Business GroupThe Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intels next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering
Degree: ME/ M.Tech./ MS (Engg/ Sciences)

Additional Degree: BE/ B.Tech (Engineering)

Experience: 8-12

Requirements

Hardware Design
Applying for this job will take you to an external site

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