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LEAD ASIC DESIGN ENGINEER STA


Source:
TIMESJOBS.COM
Location:
Bengaluru, KA
Date:
09-11-2016
Job Code:
58239127
Categories:
  • IT
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Job Details

Candidates are expected to have good hands-on experience in the following areasComplete understanding of Syn/STA concepts (Synthesis, Timing, Equivalence Checks, Extraction, Noise, Power, UPF/CPF) and various flowDevelop/Plan complete DFT/test strategy for the device as per SOWCreate DFT implementation plan, delegate to team members and trackingTest mode timing support/debug and closure at full chip levelHandle post-silicon pattern generation, Validation and ATE debug/supportUnderstanding Test/DFT modes SDCComplete familiarity of tools used in DFT implementation (DC/RC, Tk/Tmax, Virage/Mentor memory BIST, Mentor Bscan) with expertise in one of themIndependently handle IP verification strategy and implement and verify the sameGood exposure to STA tool. Assist STA team in timing closure for DFT modesGood scripting skills (TCL/Perl)Familiarity with PD concepts/flow and assist PD team if and when requiredOwn full chip responsibilitiesInteract with DM/FM, STA/PD/test/qual team to communicate work progress and closureInteract with tool vendors and debug tool related or IP related issues independentlyHave foresight into execution. Create risk mitigation plan (RMP)Participate in different project reviews. Conduct team meeting regularlyGenerate/collect feedback from team members on project/tasks flow and initiate correction/improvement in methodologyParticipate in Focal process
Degree: ME/ M.Tech./ MS (Engg/ Sciences)

Additional Degree: BE/ B.Tech (Engineering)

Experience: 7-10

Requirements

Hardware Design | Network Planning
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