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Lead Engineer STA @ US Captive


Source:
TIMESJOBS.COM
Location:
Bengaluru, KA
Date:
09-11-2016
Job Code:
58221130
Categories:
  • IT
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Job Details

Experience 4 to 8 yrsLocation -BangaloreJob Description STA (Static Timing Analysis) EngineerCan perform a full block level timing analysis.Can perform a full IP level synthesis and timing analysis.Able to setup Full chip Level Timing ConstraintCan perform timing fixes on the netlistKnowledgeable on mode analysis, case analysis and On Chip Variation(OCV) timing analysis.Competent to perform timing analysis with designs having multiple clocksknowledgeable to understand the various clock synchronization schemes for multi-clock design.Experience on multimillion Gate and complex design with multiple clocks and power domains with minimal supervision.timing closure flow with hands-on experience in formal equivalence, placement, optimization, low power checks, clock treeExperience in developing and supporting fully automated STA scripts/flowsKnowledge of commonly used clocking, low power schemes, DFT techniques are added advantage.Good control over scripting languages like PERL/TCL is MUST.Basic knowledge of networking SoCs as per our Product RequirementMail to shobhita@onssearch.in
Additional Degree: BE/ B.Tech (Engineering)

Experience: 4-8

Requirements

Hardware Design
Applying for this job will take you to an external site

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