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Principal Engineer

Bengaluru, KA
Job Code:
  • IT
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Job Details

The employee is responsible for complete physical design of multiple large & complex blocks & fullchip implementation & integration for Achronixs FPGA products in Intel s 22nm and 14nm technology nodes. The employee is expected to provide technical leadership & take ownership of multiple complex design & flow challenges, which would includeFloorplanning, Place & Route and CTS using physical design toolsPhysical verificationIntegrationPhysical Design MethodologySchedulingMentoring individualsProvide technical leadership to the teamThe employee is also expected to participate & own major parts of the flow & methodology development.The employee is expected to lead interaction with design & fabrication partners.The employee is expected to mentor other engineers & new hiresSkillsExpertise in Physical Design activities Floor-planning, CTS, P&R, Extraction, IR drop analysis, STA, Physical Verification and Signal IntegrityExpertise with Physical Design toolsA strong understanding of layout DRC rules & concepts and device identification conceptsParticipated in at least 2 tapeouts on 40nm and below, with significant experience on 28nm and below nodesStrong programming knowledge in Perl, TCL, and/or Shell ScriptingExpertise in flow developmentStrong Leadership skillsStrong communication skillsExperience/EducationPrevious experience in 4-5 VLSI projects in deep submicron technologiesExperience in 28nm or beyond is a plusExperience in custom layout is a plusExperience in Intels technology nodes is a plusExpertise in ICC & ICV is a plusPreferred BS/MS + 8-12 years of experience in physical design
Degree: ME/ M.Tech./ MS (Engg/ Sciences)

Additional Degree: BE/ B.Tech (Engineering)

Experience: 8-12


Application Programming | Software Engineer
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