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Senior Design Engineer


Source:
TIMESJOBS.COM
Location:
Bengaluru, KA
Date:
11-11-2016
Job Code:
58255526
Categories:
  • IT
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Job Details

The employee will be responsible for block-level SoC-level IP RTL design, as well as fullchip level integration RTL design for Achronixs FPGA products. The employee is expected to take independent ownership of complex design challenges, which will/may includeMicro-architecture developmentRTL code developmentTiming constraints development with STA teamPost-Si bring-upFunctional verification at module-levelThe employee is also expected to participate regularly in interactions with global teams spanning System Engineering, Software & Product EngineeringSkillsStrong background in micro-architecture development and RTL codingStrong knowledge of DDR/GPIO PHYs and memory controllers, or SerDes and communication PHYs/MACs is a plusExperience with system level performance modeling is a plusExperience with synthesis & STA is a plusExperience with post-Si bring-up & debug is a plusAutomation & scripting experienceExcellent verbal and written communication skillsPro-active mindset, looking to learn and develop new technologiesAbility to work in a dynamic & fast-paced environmentExperience/EducationPreferred BS/MS + 2-4 years of experience in RTL design & verificationPrevious experience in 2-3 product developmentsExperience designing with SerDes and/or DDRGood working knowledge of industry standard tools & methodologies such as VCS, nLint, Megallan, Verdi & OVM/UVM
Degree: ME/ M.Tech./ MS (Engg/ Sciences)

Additional Degree: BE/ B.Tech (Engineering)

Experience: 2-4

Requirements

H/W Installation/Maintenance | Hardware Design | RF Engineering
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