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Senior Verification Engineer

Secunderabad, Telangana
Job Code:
  • Manufacturing & Production
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Job Details

Plan the verification of complex digital systems by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.Create a constrained-random verification environment using SystemVerilog and UVM.Identify and write all types of coverage measures for stimulus and corner-cases.Debug tests with design engineers to deliver functionally correct design blocks.Close coverage measures to identify verification holes and to show progress towards tape-outRequirements 5+ years of experience in the verification of complex digital systems BS degree in Computer Science or Electrical EngineeringExperience in the verification of designs such as CPUs, networking or peripheral controllers.Experience with verification methodology such as UVM/OVM/VMM. Experience with System Verilog, SVA and functional coverage. Experienced with the full verification life cycle Knowledge of and experience with industry-standard simulators, revision control systems and regression systems. Strong communicator and team player. Strong problem solver Desired Skills Experienced in the design and the use of assertion languages RTL, System Verilog, Assertions (SVA), VHDL, Verilog, etc. Solid knowledge and experience of Test Bench development in System Verilog Experienced with verification methodologies like UVM and Power Aware verification with UPF/CPF Experience in behavioral model development Knowledge of wireless/wired communications and protocols is a plus, as are good written and oral skills
Degree: M.Com. (Commerce) | M.Pharm. (Pharmacy) | M.Sc. (Science) | MA (Arts) | MBA/ PGDM | MCA/ PGDCA

Additional Degree: BE/ B.Tech (Engineering)

Experience: 5-10


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