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SoC Verification Engineer

Bengaluru, KA
Job Code:
  • IT
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Job Details

Job Description Oversees definition, design, verification, and documentation for SoC (System on a Chip) development. Determines architecture design, logic design, and system simulation. Defines module interfaces/formats for simulation. Performs Logic design for integration of cell libraries, functional units and sub-systems into SoC full chip designs, Register Transfer Level coding, and simulation for SoCs. Contributes to the development of multidimensional designs involving the layout of complex integrated circuits. Performs all aspects of the SoC design flow from high-level design to synthesis, place and route, timing and power to create a design database that is ready for manufacturing. Analyzes equipment to establish operation infrastructure, conducts experimental tests, and evaluates results. May also review vendor capability to support development.QualificationsJob DescriptionSoC Verification Engineers are responsible for the verification or pre-silicon validation of the SoC designs. In general, candidates must have experience performing SoC verification based on architectural/micro-architectural specification review and analysis followed with definition of verification requirements. ResponsibilitiesCandidates will be required to Work with other verification engineers, design engineers, micro-architects, integration experts, architects, and firmware engineers to develop and review high quality verification plans.Define, implement, and deploy verification capabilities, methodologies, and process improvements aligned to long term strategic interests of the team and technical requirements. Develop test plans, coverage plans tests and test bench components -- BFMs, checkers, coverage bins, reference models and scoreboards -- from high level verification plans.Document specifications of VIPS, test bench, and reference models. Work closely with design and architecture teams to review and refine test and coverage requirements.Run regressions and debug failing tests. Minimum RequirementsCandidates must possess a Bachelor or a Master's degree in Electrical or Computer Engineering fields. 9+ years' experience in ASIC logic verification9+ years' experience programming in an object oriented language such as System Verilog C++ and/or Specman 9+ years' experience with RTL simulators9+ years' experience debugging in RTL Additional Preferred RequirementsExperience with Synopsys Verilog Compiler Simulator (VCS) Experience with VerilogExperience with debug tools such as Verdi Experience with SoC integration and validation
Additional Degree: BE/ B.Tech (Engineering) | B.Sc. (Science)

Experience: 9-14


H/W Installation/Maintenance | Hardware Design
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