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Sr Engineer DFT


Source:
TIMESJOBS.COM
Date:
13-11-2016
Job Code:
58268672
Categories:
  • IT
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Job Details

Should complete Scan insertion, Scan compression for full chip level.Boundary scan (AC and DC), JTAG and TAP insertion.Expertise in Memory BIST insertion using SMS 5.0 for Virage memory.The engineer should be able to plan, partition the test logic for the full chip design.Generate ATPG vectors for at-speed and scan clocks and simulate it at various stages of physical design closure.Work with timing team [Physical Design and STA] on Test mode constraints development and Test mode timing closure.Understand different IP test requirements and come up with IP test wrappers and verify them.Patterns generation to bring up ATE program upon parts arrival.The candidate should be able to perform at least one of the following tasks Formal verification for full chip test logic, run power integrity checks for the design with UPF.Work with product engineers for analyzing any returned parts and feeding this information back to test insertion for future program or adjusting pattern generation of failed parts.Work with product engineers for yield analysis and root cause the issues. Must be technically adept, a strong team player and have demonstrated experience of taping out in challenging timelines for complex and relevant SoCs. The candidate needs to have excellent interpersonal and communication skills and good problem solving skills.Qualifications The engineer should be at-least BE with 6 to 9 years of relevant VLSI experience in DFT, silicon debug. Strong individual contributor needed to support product line ASIC design. The candidate will work on leading edge storage solutions in an ASIC, full custom and SoC design.The candidate should have demonstrated experience/exposure to DFT for high-speed digital designs, expected to be high volume production with yield sensitivity.Domain Expertise DFT techniques TAP, BSCAN, AC BSCAN, Scan chain insertion, compression, ATPG generation and Memory BIST, memory soft repair, BISR, test time optimization.Complete understanding of defect modeling and fault tolerant design concepts, fault, test coverage analysis and improvement.Conversant in STA, Should have experience with formal verification and UPF based low power flows.Fluency in RTL using VHDL and VerilogExposure to ATE and silicon debug, yield analysis, shmoo plots, etc.Technology node 28nm / 40nmTools Synopsys SMS, DFT Max, Tetra-Max, Si_Debug, Prime-Time, Design Compiler Ultra, Formality, MVRC NCSIM, VCS.Mentor TAP insertion, Boundary scan. TestKompress.IP PCIE*, Flash controllers (ONFI*), DDR2, 3, 4, GPIO, PLL, DLL, CPR sensors, etc.Expect expertise in scripting languages preferably Tcl.
Degree: MCA/ PGDCA | ME/ M.Tech./ MS (Engg/ Sciences)

Additional Degree: BE/ B.Tech (Engineering) | BCA (Computer Application)

Experience: 6-9

Requirements

H/W Installation/Maintenance | Hardware Design
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