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Sr Engineer : Physical Design


Source:
TIMESJOBS.COM
Date:
09-11-2016
Job Code:
58233170
Categories:
  • IT
Applying for this job will take you to an external site
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Job Details

Should be able to own tasks of PnR , bumping, padring planning, partitioning, pin optimization, floor plan, power plan placement, top level CTS, routing and chip level timing closure using industry standard EDA tools, along with related backend activities in demanding schedule deadlineOwn parasitic extraction, timing closure in PD for hierarchical design and signal integrity sign-off as needed.The candidate should be able to perform at least one of the following tasksShould be able to run and analyze STA for the design.Should be able to run DRC, LVS, Antenna, DFM checks at full chip level.Should be able to work on EM / IR analysis for full chip flat designs. Interface with packaging team and IP team for bumping / bonding activities and IP integration.Qualifications The engineer should be at-least BE with 6 to 8 years of relevant VLSI physical design experience. Strong individual contributors needed to support product line ASIC design. The candidate will work on leading edge storage solutions in an ASIC, full custom and SoC design. The candidate should have demonstrated experience/exposure to high-speed digital physical design and physical verification including ASIC through semi-custom high-speed digital designs from synthesis through tape out. Domain ExpertiseHierarchical and flat level physical design flow which includes, bumping, padring planning, partitioning, pin optimization, floor plan, power plan placement, top level CTS, routing and chip level timing closure, Should be able to run DRC, LVS, EM, IR, DFM. Low power design with UPF.Technology node 28nm / 40nmTools Synopsys tool for PnR and timing closure.Mentor Calibre for physical verification, Ansys RedHawk for IR (static, dynamic) and EM analysis, Additional Exposure to Encounter is desirable. Custom routes design using Industry standard tools. ICC is preferred. Knowledge of Virtuoso is desired.Must be technically adept, a strong team player and have demonstrated experience of taping out in challenging timelines for complex and relevant SoCs. The candidate needs to have excellent interpersonal and communication skills and good problem solving skills.
Additional Degree: BE/ B.Tech (Engineering)

Experience: 6-8

Requirements

H/W Installation/Maintenance | Hardware Design
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