Sign In
 [New User? Sign Up]
Mobile Version

Sr Engineer STA

Job Code:
  • IT
Applying for this job will take you to an external site
  • Shortlist
  • Email Friend
  • Print

Job Details

The candidate will work closely in a DI team for synthesis and STA of SoCs. The candidate will be responsible for following tasks.Will be responsible for synthesis for hierarchical designs which includes feedback for RTL optimization and constraints clean-up.Will be responsible for STA for hierarchical designs, recommending the timing closure methodology for a given STA sign-off. This STA involves multi-mode, multi-corner scenarios with OCV/AOCV/SI, what-if analysis, timing-ECO generation to fix timing/drc violations.Hands-on usage and creation of ETM models used in Hard Macros.Interface with physical design, IP team and RTL design team to debug timing issues and sign-off timing checks. The candidate should be able to perform at least one of the following tasksIO timing closure for timing critical interfaces such as flash, PCIE and DDR.Perform glitch analysis, SI analysis for interfaces such as DDR and flash.Formal verification for the blocks.Run power integrity checks for the design with UPF. Must be technically adept, a strong team player and have demonstrated experience of taping out in challenging timelines for complex and relevant SoCs. The candidate needs to have excellent interpersonal and communication skills and good problem solving skills.
Degree: M.Com. (Commerce) | M.Pharm. (Pharmacy) | M.Sc. (Science) | MA (Arts) | MBA/ PGDM | MCA/ PGDCA

Additional Degree: BE/ B.Tech (Engineering) | BCA (Computer Application)

Experience: 5-8


Customer Support | H/W Installation/Maintenance | Hardware Design
Applying for this job will take you to an external site


© Copyright 2015 Al Nisr Publishing LLC - powered by Gulf News