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Sr. Staff Engineer DFT


Source:
TIMESJOBS.COM
Date:
09-11-2016
Job Code:
58239141
Categories:
  • Manufacturing & Production
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Job Details

Skills and knowledge base requirements include Relevant VLSI experience in DFT & Silicon debug.Must have demonstrated experience of taping out in challenging timelines for complex and relevant SoCs.Should have demonstrated experience/exposure to DFT for high-speed digital designs, expected to be high volume production with yield sensitivity.Expert in DFT techniques TAP, BSCAN, AC BSCAN, Scan chain insertion, compression, ATPG generation and Memory BIST, memory soft repair, BISR, test time optimization.Complete understanding of defect modeling and fault tolerant design concepts, fault, test coverage analysis and improvement.Conversant in STA, Should have experience with formal verification and UPF based low power flows.Fluency in RTL using VHDL and VerilogTechnology node 28nm / 40nmExpert in Synopsys Tools SMS, DFT Max, Tetra-Max, Si_Debug, Prime-Time, Design Compiler Ultra, Formality, MVRC NCSIM, VCS.Expert in Mentor Tools TAP insertion, Boundary scan. TestKompress.SAS/SATA, PCIE*, Flash controllers (ONFI*), DDR2, 3, 4, GPIO, PLL, DLL, etc.Expert in scripting languages preferably Tcl. Highly Desirable Skills & Knowledge includeAbility to interface effectively with many diverse groups and people across multiple locations.Candidate needs to be highly motivated and be able to independently drive own self to excellence.Presentation and negotiation skills are critical.Position responsibilitiesScan insertion, Scan compression.Boundary scan (AC and DC), JTAG and TAP insertion.Memory BIST insertion using SMS 5.0 for Virage memory.Should be able to plan, partition the test logic for the full chip design.Generate ATPG vectors for at-speed and scan clocks and simulate it at various stages of physical design closure.Work with timing team [Physical Design and STA] on Test mode constraints development and Timing closure.Understand different IP test requirements and come up with IP test wrappers and verify them.Formal verification for full chip test logic, run power integrity checks for the design with UPF.Work with product engineers for analyzing any returned parts and feeding this information back to test insertion for future program or adjusting pattern generation of failed parts.These activities must be worked in a cross functional team setting and therefore require the candidate to have excellent communication and interpersonal skills. May coordinate activities of other personnel.Qualifications BSEE or BSCS or equivalent and 12+ years of experience or MS and 10+ years of experience in DFT
Degree: M.Com. (Commerce) | M.Pharm. (Pharmacy) | M.Sc. (Science) | MA (Arts) | MBA/ PGDM | MCA/ PGDCA

Additional Degree: BE/ B.Tech (Engineering)

Experience: 12-17

Requirements

Software Engineer | Systems Programming
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