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Staff Engineer


Source:
TIMESJOBS.COM
Date:
19-11-2016
Job Code:
58324283
Categories:
  • IT
Applying for this job will take you to an external site
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Job Details

Skills and knowledge base requirements includeExperience with design flows utilizing Unix, Linux, Synopsys Tools and Verilog or System Verilog.Experience running large scale synthesis and static timing analysis in deep submicron design technologies.Expertise in scripting skills in Perl, TCL/TK, and C shell.Ability to work with ASIC teams and other integration team members.Capable of assisting in determining methods and procedures to use on new projects.Candidate must possess passion and commitment for completing projects on time.Highly Desirable Skills & Knowledge includeAbility to interface effectively with many diverse groups and people across multiple locations.Candidate needs to be highly motivated and be able to independently drive own self to excellence.Presentation and negotiation skills are critical. Position responsibilitiesAreas of responsibility include logic synthesis, constraint development, static timing analysis, formal verification and low power implementation.Responsibilities will also include evaluation of the back end flow and results, including place and route, CTS, timing and power utilization.These activities must be worked in a cross functional team setting and therefore require the candidate to have excellent communication and interpersonal skills. May coordinate activities of other personnel.
Degree: MCA/ PGDCA | ME/ M.Tech./ MS (Engg/ Sciences)

Additional Degree: BE/ B.Tech (Engineering) | BCA (Computer Application)

Experience: 8-10

Requirements

Configuration/Release Mgmt | System Administration
Applying for this job will take you to an external site

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