Sign In
 [New User? Sign Up]
Mobile Version

Staff Engineer STA & Synthesis

Job Code:
  • IT
Applying for this job will take you to an external site
  • Shortlist
  • Email Friend
  • Print

Job Details

The candidate will work closely in a DI team for synthesis and STA of SoCs. The candidate will be responsible for following tasks.Will be responsible for synthesis for full chip hierarchical designs which includes feedback for RTL optimization and constraints clean-up.Will be responsible for STA for full chip hierarchical designs, recommending the timing closure methodology for a given STA sign-off. This STA involves multi-mode, multi-corner scenarios with OCV/AOCV/SI, what-if analysis, timing-ECO generation to fix timing/drc violations.Will be responsible for IO timing closure for critical interfaces such as flash, PCIE and DDR.Will have to co-ordinate with physical design, IP team and RTL design team to debug timing issues and sign-off timing. The candidate should be able to perform at least one of the following tasksHands-on usage and creation of ETM models used in Hard Macros.Perform glitch analysis, SI analysis for interfaces such as DDR and flash.Formal verification for the blocks.Run power integrity checks for the design with UPF.Lead/mentor team of junior engineers. Must be technically adept, a strong team player and have demonstrated experience of taping out in challenging timelines for complex and relevant SoCs. The candidate needs to have excellent interpersonal and communication skills and good problem solving skills. QualificationsThe engineer should be at-least BE with 9 to 12 years of relevant VLSI experience in synthesis and STA. Strong individual contributors needed to support product line ASIC design. The candidate will work on leading edge storage solutions in an ASIC, full custom and SoC design. The candidate should have demonstrated experience/exposure to synthesis and STA for high-speed digital designs.Domain ExpertiseSynthesis for full chip hierarchical design with zero-wireload and physical.STA for full chip hierarchical design for functional and test modes with timing DRC fixes.Experience in low power design and signal integrity.Experience in physical design is an added advantage.Conversant about timing closure in physical design and timing-ECO generation.Should have experience with formal verification and power analysis flow.Technology node 28nm / 40nmToolsSynopsys PrimeTime, Design Compiler Ultra, Formality, MVRC.InterfacesPCIE*Flash controllers (ONFI*)DDR2,3,4GPIOExpect expertise in scripting languages preferably Tcl.
Degree: MCA/ PGDCA | ME/ M.Tech./ MS (Engg/ Sciences)

Additional Degree: BE/ B.Tech (Engineering) | BCA (Computer Application)

Experience: 9-12


Customer Support | H/W Installation/Maintenance | Hardware Design | Network Planning
Applying for this job will take you to an external site


© Copyright 2015 Al Nisr Publishing LLC - powered by Gulf News