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STANDARD CELL LAYOUT


Source:
TIMESJOBS.COM
Location:
Bengaluru, KA
Date:
15-11-2016
Job Code:
58291073
Categories:
  • IT
  • Manufacturing & Production
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Job Details

Job Description& Responsebilities3 8 yrs Hands-on experience layout of digital ASICs in leading edge CMOS processes 28nm, 20nmTools Cadence (preferably 6.1* Open Access version), Cadence VXL, Mentor Graphics Calibre verification suite, Calibre RVE
Additional Degree: BE/ B.Tech (Engineering)

Experience: 3-8

Requirements

Customer Support | Embedded Technology | Hardware Design
Applying for this job will take you to an external site

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