FIND YOUR DREAM JOB

Sign In
 [New User? Sign Up]
Mobile Version

Technical Lead Physical Verification Full Chip


Source:
TIMESJOBS.COM
Location:
Bengaluru, KA
Date:
11-11-2016
Job Code:
58252262
Categories:
  • IT
Applying for this job will take you to an external site
  •  
  • Shortlist
  • Email Friend
  • Print

Job Details

Working on Physical Verification for ASICs at Block level and Full chip level in Physical design flow. Candidate should have done at least 5 Tape out using Physical Verification in last 5 Years. Should be able to resolve Design Rule Checking (DRC), Layout vs. Schematic (LVS), antenna effects Antenna Rule Checking errors in Layout database. Debug, report and close all Violations for DRC, LVS, ERC, ARC including density verification at the full chip level. Work on violations waivers with chip lead/Team. Experienced with Scripting languages and working with Calibre from Mentor graphics is must. Expertise with Synopsys ICC, PT-PTSI, DC, OR EDS/SoCEncounter.
Degree: ME/ M.Tech./ MS (Engg/ Sciences)

Additional Degree: BE/ B.Tech (Engineering)

Experience: 7-12

Requirements

Hardware Design | Network Planning
Applying for this job will take you to an external site

FEATURED JOBS

© Copyright 2015 Al Nisr Publishing LLC - powered by Gulf News